Space instrumentation has to operate in hazardous high-radiation environments. Depending on a particular mission this may encompass solar and cosmic radiation as well as trapped high energy electron & proton belts in the vicinity of planetary bodies. The inability to replace hardware failures on satellites means very rigorous instrument design and component selection is needed to ensure reliability during the mission timeline. Semiconductor circuits and devices, including complementary metal-oxide-semiconductor (CMOS) devices are often part of systems and devices used in such harsh environments. Other harsh environments include high altitude flight, nuclear power stations and battlegrounds. However, semiconductors are prone to damage from radiation. This is due to the very nature of semiconductors—typically small band gap materials operating with limited numbers of charge carriers. The effect of radiation in semiconductors is a complicated subject but generally speaking three effects can be identified:                1. Displacement Damage is cumulative long-term non-ionizing damage due to high energy particles. The impact of a high energy particle can create vacancy sites where recombination can occur. This can reduce the device performance and may eventually result in a non operation.        2. Short-term effects, such as Single Event Effects (SEEs) (e.g. a Single Event Upset (SEU) or a single event transient (SET)): this can cause a bit flip (i.e. change in logic state) in an integrated circuit, thereby causing a loss of information. The severity of this effect depends on the type of SEE. In some examples, an SET may propagate through a circuit and lead to an SEU that changes the logic state. Another short-term effect, the dose ray effect, is caused by exposure of an entire integrated circuit to a flood of radiation, such as x-rays. This effect is typically related to short bursts (typically of the order of nanoseconds to milliseconds) of radiation, which can cause temporary, and in some cases permanent, failure of integrated circuits.        3. Total ionization damage where the impact of high energy particles results in electron-hole pair creation. In the case of powered metal-oxide-semiconductor field effect transistors (MOSFETs), electron diffusion can enhance conduction which can lead to permanent turn-on & associated high current consumption (known as ‘latch up’) resulting in device burn out and potential damage elsewhere. A cumulative measure of the damage is the Total Ionizing Dose (TID). Accumulation of radiation dose can trap charge carriers within semiconductor devices, for example, trapping generated charge in insulating SiO2 regions of a device. This can cause shifts of the threshold voltage, leakage currents, timing skew and lead to permanent, functional failures of the circuit.        
Radiation hardening by design (RHBD) employs layout and circuit techniques to mitigate TID and single-event effects, including single-event latchup (SEL). As mentioned above, a primary TID effect is positive charge accumulation in isolation oxides, shifting the threshold voltages of devices associated with the circuit, including parasitic devices. Transistor layouts that provide TID and SEL hardness are typically larger than the conventional two-edge transistors used for non-hardened ICs and increase active power as well as leakage over a non-hardened design. NMOS transistors are usually the most sensitive part of CMOS circuits to total dose effects, and efforts have been made to harden CMOS devices and circuits against total dose effects. Many techniques add further complex processing steps to the manufacturing process. Furthermore, the use of error detection and correction techniques can result in larger circuit sizes and slower performance of semiconductor circuits. Triple redundancy techniques or temporal sampling based design usually result in higher power and/or lower performance (e.g. slow clock rates).
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well known features and techniques may be omitted to avoid unnecessarily obscuring of the drawings. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of different embodiments.
The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the present disclosure are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “include,” and “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in orientations other than those illustrated or otherwise described herein.
The terms “couple,” “coupled,” “couples,” “coupling,” and the like should be broadly understood and refer to connecting two or more elements, electrically, mechanically, and/or otherwise, either directly or indirectly through intervening elements. Coupling may be for any length of time, e.g., permanent or semi-permanent or only for an instant. The absence of the word “removably,” “removable,” and the like near the word “coupled,” and the like does not mean that the coupling, etc. in question is or is not removable.